1. Field of the Invention
The present invention relates to a semiconductor memory device, more specifically to a CMOS (Complementary Metal Oxide Semiconductor) memory which is designed to cope with the problem of hot carriers.
2. Description of the Related Art
In the recent design and development of DRAMs, one kind of semiconductor memories, special importance is attached to the technique of laying out row decoder sections to be as small as possible.
FIG. 17 shows an example of the core portion of a general DRAM. As shown in FIG. 17, the DRAM includes a plurality of memory cell arrays 11. Each memory cell array 11 includes a plurality of memory cells (not shown) arranged in a matrix pattern. In the example shown in FIG. 17, a plurality of word lines WL and a plurality of bit lines BL are arranged so that they intersect one another. One of the memory cells is located at the intersections between the word lines WL and the bit lines BL.
A row decoder section 21 is provided adjacent to each memory cell array 11. The row decoder section 21 includes a plurality of row decoders, by which the word lines WL arranged in rows of each memory cell array 11 are selectively driven.
A sense amplifier section 31 is arranged between two of the memory cell arrays 11 that are adjacent to each other in the row direction. The sense amplifier section 31 is used in common by the two memory cell arrays 11 adjacent to each other in the row direction. The sense amplifier section 31 includes a plurality of sense amplifiers (not shown) which sense the data read out to the bit lines BL.
A plurality of column decoder sections 41 are arrayed in the columnar direction, one for the memory cell arrays 11 of one row. Each column decoder section 41 includes a plurality of column decoders (not shown), by which the bit lines BL arranged in columns are selectively driven.
Control circuit sections 51 are provided in such a manner that one is adjacent to one row decoder section 21. Each control circuit section 51 includes a setting signal-generating circuit, a precharge signal-generating circuit, an equalize signal-generating circuit, etc. The setting signal-generating circuit is used for setting the row decoders. The precharge signal-generating circuit is used for precharging the row decoders. The equalize signal-generating circuit is used for causing a bit equalizer circuit (not shown) of the sense amplifier section 31 to perform an equalizing operation.
When a memory cell is selected in the conventional DRAM, the high-level voltage of the corresponding word line WL is increased to a boosted level (VPP), which is higher than an internal power supply voltage (VCC). By this operation, data can be read out or written at high speed. The use of the boosted voltage results in a high voltage being applied to the gate of a selected transistor connected to a word line WL. As a result, the resistance of the selected transistor lowers. In comparison with the case where the internal power supply voltage is used, a large amount of read current or write current flows to the selected transistor. In this manner, the high-speed data read or write operation is enabled.
At the same time, however, the use of the boosted voltage is accompanied by an increase in the substrate current flowing through a semiconductor substrate. This leads to an increase in the number of hot carriers generated, thus causing adverse effects on a transistor, such as an increase in the threshold voltage, a decrease in the conductance, etc.
In order to suppress the adverse effects the transistor may suffer due to an increase in the number of hot carriers (in short, to lengthen the life of that transistor), the conventional technology uses a technique of connecting a voltage-relaxing transistor in series to the transistor to which the boosted voltage is applied. The life of the transistor is closely related to the substrate current, and it is known in the art that reducing the substrate current to one tenth lengthens the life of the transistor about 1,000 times. The substrate current is an exponential function of the source-drain voltage Vds. Therefore, relaxing the voltage conditions and intensifying the electric field applied to the transistor may be the most effective way for lengthening the life of the transistor. To be more specific, where a plurality of transistors are connected in series, the voltage applied to them can be divided (resistance division), and the voltage applied to each transistor can therefore be divided.
In general, N-channel transistors are more susceptible to hot carriers than P-channel transistors. In a CMOS-type DRAM wherein both an N-channel transistor and a P-channel transistor are provided, it is effective to connect in series a voltage-relaxing transistor only to the N-channel transistor.
FIG. 18 shows an example of a row decoder section which is employed in a CMOS-type DRAM and for which the above-mentioned measure against the hot carriers is taken. In general, a row decoder section is made up of a plurality of decoder circuits (row decoders) arranged in an array, but only one decoder for selecting one word line WL will be described herein, for the sake of simplicity.
Referring to FIG. 18, the row decoder includes the following: a partial-decoder circuit 22 which decodes input addresses BX and BY; two pre-driver circuits 23 and 24 connected to the partial-decoder circuit 22 and used for sequentially inverting an output of the partial-decoder circuit 22; a latch circuit 25 which latches the output from the partial-decoder circuit 22; and a word line driver circuit 26 which drives the word line WL on the basis of an output from pre-driver circuit 24.
The partial-decoder circuit 22 is a precharge/discharge type decoder, and is made up of one P-channel transistor P11 and three N-channel transistors N11-N13. At the end of a precharge period based on input of a precharge signal PREC, the partial-decoder circuit 22 outputs, a decode signal based on the input addresses BX and BY and a multi-bit (e.g., 3-bit) setting signal SET.
The first pre-driver circuit 23 includes one P-channel transistor P12 and two N-channel transistors N14 and N15, and inverts an output of the partial-decoder circuit 22. The second pre-driver circuit 24 includes one P-channel transistor P13 and two N-channel transistors N16 and N17, and inverts an output of the first pre-driver circuit 23.
The latch circuit 25 includes one P-channel transistor P15 and two N-channel transistors N20 and N21. When the pre-charge period of the partial-decoder circuit 22 has ended and after a decode signal based on the input addresses BX and BY has been determined, the latch circuit 25 latches the decode signal and continues to latch it even after the input addresses BX and BY vary. Accordingly, the operation is controlled in accordance with the precharge signal PREC and an output from the pre-driver circuit 23.
The word line driver circuit 26 includes one P-channel transistor P14 and two N-channel transistors N18 and N19, and drives the word line WL in response to an output mwl-n from the pre-driver circuit 24.
With the above configuration, a boosted voltage VPP, which is obtained by boosting the internal power supply voltage VCC, is applied to the sources the P-channel transistors P12, P13, P14 and P15 included in the pre-driver circuits 23 and 24 and latch circuit 25 and word line driver circuit 26. In the case of this row decoder, the boosted voltage VPP is used as a power supply voltage for the pre-driver circuits 23 and 24 and word line driver circuit 26. To decrease the intensity of the electric field applied to the N-channel transistors N15, N17 and N19 of the pre-deriver circuits 23 and 24 and word line driver circuit 26, N-channel transistors (voltage-relaxing transistors) N14, N16 and N18, the gates of which are applied with the boosted voltage VPP, are connected in series to N-channel transistors N15, N17 and N19, respectively.
As described above, voltage-relaxing transistors N14, N16 and N18 are connected in series to N-channel transistors N15, N17 and N19, respectively. In this case, the maximal value of the voltages applied to the sources of N-channel transistors N15, N17 and N19 is expressed by VPP−VthN (VthN is a threshold voltage of the N-channel transistors). Therefore, the voltage Vds applied between the drain and source of each of N-channel transistors N15, N17 and N19 is smaller than the maximal value of the voltage applied to the word line WL, and the voltage difference is VthN. Hence, even if the substrate current increases, adverse effects on a transistor, such as an increase in the threshold voltage or a decrease in the conductance, can be suppressed.
FIG. 19 shows an example of a configuration of an equalize signal-generating circuit 52 of each control circuit section 51. The equalize signal-generating circuit 52 generates equalize signal eql_p on the basis of selection signal bksel_p, and is made, for example, of a CMOS inverter circuit connected between the drains of P-channel and N-channel transistors 52a and 52b for the internal power supply voltage VCC.
FIG. 20 shows an example of a configuration of a setting signal-generating circuit 53 of each control circuit section 51. The setting signal-generating circuit 53 generates setting signal SET on the basis of input addresses AX and AY and a word-line-on signal wlon. For example, the setting signal-generating circuit 53 is made of an inverter circuit 53-1 which includes a P-channel transistor 53a and an N-channel transistor 53b, and a 3-input NAND circuit 53-2 which is controlled on the basis of the input addresses AX and AY and word-line-on signal wlon. The inverter circuit 53-1 is a CMOS circuit operating on the internal power supply voltage VCC, and the drains of its P-channel and N-channel transistors 53a and 53b are connected together.
FIGS. 21A and 21B show examples of configurations of precharge signal-generating circuits 54A and 54B of each control circuit section 51. Each of the precharge signal-generating circuits 54A and 54B generates a precharge signal PREC on the basis of input addresses AX and AY, and is made, for example of the following: a 2-input NAND circuit 54-1, a level shifting circuit 54-3 (VCC→VPP) and another inverter circuit 54-4. Inverter circuit 54-4 includes one P-channel transistor 54a and two N-channel transistors 54b and 54c, and is a CMOS circuit operating on the boosted voltage VPP.
In the case of precharge signal-generating circuit 54A, the gate of N-channel transistor 54c constituting part of inverter circuit 54-4 is applied with boosted voltage VPP as a fixed voltage. In the case of precharge signal-generating circuit 54B, the gate of N-channel transistor 54b constituting part of inverter circuit 54-4 is applied with boosted voltage VPP as a fixed voltage. Normally, each control circuit section 51 is provided with either one of precharge signal-generating circuit 54A or 54B.
As described above, the layout of the row decoder sections 21 is made as small as possible by including circuits 53, 54A and 54B, which are used for controlling a given row decoder, in the control circuit section 51 adjacent to that row decoder section 21. In addition, circuit 52, which controls the sense amplifier section 31, is also included in that control circuit section 51. As can been seen from this, a large number of circuits are included or laid out within the control circuit section 51, for the purpose of a high-speed operation of chips.
However, with the recent trend toward the miniaturization of DRAMs, the area that can be earmarked for the control circuit section 51 is far narrower than before. Increasing the area of the control circuit section 51 is against the miniaturization of DRAMs. Eventually, the chip size of a DRAM is determined not by the size of the row decoder section 21 but by the area of the control circuit section 51.